Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof

ABSTRACT

A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

RELATED APPLICATION DATA

[0001] The present application claims priority to Japanese ApplicationNo. P2000-122112 filed Mar. 24, 2000, which application is incorporatedherein by reference to the extent permitted by law.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a chip-like electronic componentsuitable for use in the manufacture of a semiconductor device and amethod of manufacturing the same, and in particular, it relates to apseudo wafer for use in the manufacture of the same and a methodtherefor.

[0003] Recently, demands for a more compact, thinner and lightweightdesign of a portable electronic device which is typically represented bya digital video camera, a digital portable telephone, a note-sizepersonal computer and the like are growing, thereby it is becoming amost important key point how to improve a surface packaging density ontheir semiconductor parts. For this purpose, a development of a morecompact CSP (Chip Scale Package) in place of package ICs (QFP (Quad flatpackage) or the like) and a proliferation of a bare chip packaging basedon the flip chip method which is now partially adopted and may lead toan ultimate semiconductor high density packaging technology are stronglydesired.

[0004] By way of example, as a typical bump forming technique in theabove-mentioned flip chip packaging method, there are a method forforming Au bumps on an Al electrode pad by using the Au-stud bump methodor the electroplating method, and a method for forming solder bumps inbatch by using the electroplating method or the vapor deposition method.However, in a commercial application where a low cost flip chippackaging is preferred, it is advantageous not to form bumps after thechip is prepared as in the Au stud bump method, but to form bumps inbatch in its preceding stage of wafer.

[0005] This wafer batch processing method described above clearlyindicates a trend of technology in the future in consideration of arecent advancement of large scaled wafers (from 150 mmφ to 200 mmφ andto 300 mmφ), and an increasing number of chip connection pins in LSIs(large scaled integrated-circuits).

[0006] Conventional bump forming methods will be described in thefollowing.

[0007]FIG. 9 is an example showing an Au stud bump 24. On a surface ofan Al pad 55 formed on a semiconductor chip 25 which is diced from awafer there is formed the Au stud bump 24 using a wire bonding method.FIG. 10 shows an example in which a silicon substrate (wafer) 51 having,for example, an input/output circuit 22 and a device region (memory) 23formed thereon, is processed in batch so as to form solder bumps 62 inits wafer level. By way of example, reference numeral 21 depicts ascribe line.

[0008] Further, FIGS. 11A-11E show steps of forming bumps on a wafer inbatch in combination of Ni electroless plating and solder paste printingmethods in order to reduce the cost of manufacture. FIG. 11A depicts asilicon substrate (wafer) having an SiO₂ film formed thereon, and FIG.11B depicts an enlarged part of a chip portion including its electrodes.In FIGS. 11A and 11B, numeral 51 depicts an Si substrate (wafer), 55depicts an Al electrode pad, and others depict a SiO₂ film and apassivation film comprising Si₃N₄ film, SiO₂ film or a polyimide film.

[0009] In FIG. 1C, exclusively on a perforated upper surface of the Alelectrode pad 55, an Ni electroless plating layer (UBM: under bumpmetal) is formed selectively by the Ni electroless plating method. ThisNi electroless plating layer serving as a UBM for supporting electricconnection between the Al electrode pad 55 and the solder bump can beformed easily by the steps of pretreating the Al electrode pad 55 with aphosphoric acid etching solution, substitution-precipitating Zn by a Znprocessing, and dip-coating in a Ni—P plating vessel.

[0010]FIG. 11D shows a state in which a solder paste 59 is transferredonto the Ni electroless plating layer (UBM) through a metal screen mask52 by a printing method. FIG. 11E shows a state in which the solderpaste 59 is fused by a wet back method (hot fusing) to form a solderbump 62. Thereby, without use of a photo processing, the solder bump 62can be formed easily by using the Ni electroless plating method and thesolder paste screen printing method, or the like.

[0011] On the other hand, the CSP which is an approach to a high densitypackaging of LSIs by minimizing respective chips thereof is comprised ofseveral common circuit blocks as viewed from the standpoint of a digitaldevice circuit block diagram, and there is emerging such a process toprovide these common circuit blocks in a multi package or in a MCM(multi chip module). Provision of SRAM (static RAM), flash memory and amicrocomputer in one chip package in a digital portable telephone is oneexample thereof.

[0012] This MCM technology is expected to show a significant advantagealso in a one-chip system LSI of a recent development. Namely, whenintegrating memory, logic and analog LSIs on one chip, different LSIfabrication processes must be handled in a same wafer processing step,thereby substantially increasing the number of masks and processingsteps, and its TAT (turnaround time) for development being prolonged.Also, a low yield in production resulting from the increased steps ofprocessing is a serious problem which cannot be ignored.

[0013] For this reason, it is considered to be promising that respectiveLSIs are fabricated discretely, then they are packaged in an MCM. Anexample of such MCM packaging is shown in FIGS. 12A and 12B.

[0014]FIGS. 12A and 12B show a wire-bonding method whereby each chip 62mounted on a circuit substrate 60 is electrically connected using a wire61 therebetween. Further, FIGS. 13A-13C show a flip chip method wherebyeach chip 64 is connected to an electrode 63 on a circuit substrate 60in a state of facedown. For the purpose of a more compact and thinnerdesign of the device, the flip chip method indicated in FIGS. 13A-13C isconsidered to be advantageous. Further, for minimization of connectingwire length necessary for a faster speed in the future, and inconsideration of impedance variations in respective connections, theflip chip method is considered to take over.

[0015] For the MCM using the flip chip method, there are proposedvarious connecting methods including such one that forms Au-stud bumpson a surface of an Al electrode pad 55 provided on each LSI of aplurality of different types of LSIs, and electrically connects with itscircuit substrate via an anisotropic conductive film (ACF), anothermethod by a press bonding using a resin paste, and other ones that useplated Au bumps, Ni electroless plated bumps, soldered bumps or the likeas its bumps. FIG. 13C shows an example which ensures a lower electricresistance connection to the substrate 60 by means of an intercalationbonding via a solder bump 65.

[0016] The above-mentioned respective bump-forming methods have beencompleted already and started to be used for mass production. Forexample, the Au stud bump 24 indicated in FIG. 9 is formed by a methodof forming a bump per chip. This method of forming a bump per chip iswidely used as a simple bump forming method using existing facilities,however, there is a problem that as the number of termination pinsincreases, the cost of forming bumps will increase accordingly.

[0017] Further, in a recent trend of a lower voltage driving of LSIs,because of a problem of a voltage drop in an Al wiring layer, aprovision of an area pad not limiting to a peripheral electrode pad butincluding additional electrode pads also on active elements is required.However, the Au stud bump 24 in FIG. 9 is not suitable for use as thisarea pad in consideration of a bonding load and a susceptibility todamage. Still further, there is such a problem that a packaging of Austud bump chips is done by press bonding of a piece by piece basis, andhas a difficulty of mounting on both surfaces.

[0018] On the other hand, the wafer batch solder bump forming method isadvantageous in terms of packaging because it can be applied to theprovision of the area pad, and enables a batch reflow or a double sidemounting. However, it has a disadvantage when applying to the processingof a leading-edge wafer which normally has a low yield of productionbecause a cost of production per non-defective chip will substantiallyincrease.

[0019] Namely, with reference to FIG. 14, which indicates asemiconductor wafer 53 fabricated by a conventional wafer batchprocessing, nevertheless a high yield of production is required for theleading-edge LSIs, the number of defective chips 20 partitioned by ascribe line 21 and marked with “x” is actually greater than the numberof non-defective chips 3 marked with “o”.

[0020] Further, there has been such a problem that if bare chips arepurchased from external manufacturers or venders, it is extremelydifficult to form bumps on them due to a varied design specification.Namely, although the above-mentioned two types of bump forming methodshave their own merits, they cannot be used in all fields, but areactually used individually taking the most use of their own merits. Thewafer batch bump forming method which has a high yield is advantageousfor use in such a case where the number of terminals accommodated withina single wafer is large (for example, 50000 terminals/wafer), or forforming low damage bumps applicable to the area pad. Further, the Austud bump is advantageous for use in a bump treatment per chip in a casewhere the bare chips are purchased by lot, or for a simple bumptreatment.

[0021] Still further, when the semiconductor wafer 53 indicated in FIG.14 is diced along the scribe line 21, a damage such as a stress or acrack occurs in the chip due to its dicing, which may lead to a failure.Furthermore, if a process of forming solder bumps in batch on thesemiconductor wafer 53 which includes both the non-defective chips 3 andthe defective chips 20 is allowed to proceed, the process applied to thedefective chips 20 is wasted, thereby increasing the cost ofmanufacture.

[0022] In Japanese Patent Application Publication Laid-Open Hei9-260581, a method of forming a wiring layer for interconnection betweendevices is disclosed whereby a plurality of semiconductor chips arefirmly bonded on a silicon wafer, embedded into a resin formed on asubstrate made of alumina or the like under pressure, then peeled off soas to provide a flat wafer surface and form the wiring layer forinterconnection between the devices on this flat wafer surface byphotolithography.

[0023] According to this conventional method, it is proposed that awafer batch processing becomes possible and a low cost manufacturethereof by a merit of mass production is attained. However, becausethere exists a hard substrate made of alumina described above under thebottom surface of each semiconductor chip arrayed on the wafer, at thetime of scribing and cutting into a dice, the hard substrate presentunder the bottom surface of the chip must be cut together with the resinbetween adjacent chips, thereby likely to damage a cutter blade. Inaddition, although the sidewalls of the chip are covered with the resin,there exists only the hard substrate different from the resin on thebottom surface thereof, therefore, there is such a problem that thebottom surface of the chip is not protected effectively and adhesiontherebetween is weak.

SUMMARY OF THE INVENTION

[0024] The present invention is contemplated to solve theabove-mentioned problems associated with the conventional art, and toprovide a chip-like electronic component such as a semiconductor chipwhich is comprised of leading-edge LSIs or bare chips even if they arepurchased from outside, and can be mass-produced at a high yield, lowcost and high reliability.

[0025] The present invention is directed to chip-like electroniccomponents such as semiconductor chips, wherein each of them has atleast its electrodes formed exclusively on one surface thereof, all therest of its surfaces without the electrodes are covered continuouslywith a protective substance and a pseudo wafer, which is comprised of aplurality and/or a plurality of different types chip-like electroniccomponents bonded spaced apart from each other by the protectivesubstance which is coated continuously therebetween and on their bottomsurfaces.

[0026] According to another aspect of the invention, a method ofmanufacturing of the pseudo wafer is provided, which is comprised of thesteps of: pasting an adhesive material on a substrate, retaining anadhesive strength prior to its processing and losing the adhesivestrength post its processing; fixing a plurality and/or a plurality ofdifferent types of semiconductor chips on this adhesive material withtheir surfaces having electrodes facing downward; coating a protectivematerial on a whole portion of the rest of the surfaces of the pluralityand/or the plurality of different types of semiconductor chips includinginterspatial gaps therebetween; applying a predetermined processing tothe adhesive material so as to lower the adhesive strength thereof; andpeeling off the pseudo wafer having these semiconductor chips fixedthereon. In addition, a method of manufacturing of a chip-likeelectronic component is provided, which is comprised of the step ofcutting off the protective material between respective semiconductorchips of the plurality and/or the plurality of different types ofsemiconductor chips on the wafer so as to separate and provide adiscrete semiconductor chip or a chip-like electronic component.

[0027] According to the present invention, because the portions of thechip-like electronic component such as the semiconductor chip or thelike (hereinafter explained with reference to the semiconductor chip)other than its surface provided with electrodes, namely, the side walland the bottom surface of the chip, are protected continuously with aprotective material, the chip is ensured to be protected in its postchip handling, thereby facilitating its handling and enabling anexcellent package reliability to be obtained.

[0028] Further, by pasting on a substrate solely and only non-defectivechips which are diced from a semiconductor wafer and selected, coatingthem wholly with the protective material, then peeling from thesubstrate, a pseudo wafer is obtained as if comprising completely ofnon-defective chips. Therefore, a wafer batch bump treatment for thesenon-defective chips becomes possible, thereby allowing to form bumpchips at a lower cost, and when dicing respective semiconductor chipsfrom the pseudo wafer, the portion-of the protective material, which iseasy to cut, between adjacent chips is cut along the scribe line withoutcausing any adverse effect (such as strain, burr, crack and the like) tooccur on each semiconductor chip itself. In addition, because thesidewall and the bottom surface of the chip are coated with theprotective material such as a passivation film, an Ni electrolessplating process can be applied as well. Further, not only wafers ofin-house product but also bare chips purchased from the othermanufacturers are allowed to be subjected to the solder bump treatmentlikewise and easily. By way of example, it is becoming a rare case thatall of a plurality of different types of LSI chips to be packaged in anMCM are supplied from a same semiconductor manufacturer because of anincreasing burden for investing on several leading edge semiconductorproduction lines simultaneously. Therefore, by opting not to purchase awhole bunch of chips of SRAMs, flash memories, microcomputers or evencentral processor units (CPUs) from the same semiconductor manufacturer,but to purchase them separately from different chip manufacturers whoare most specialized in any one of these leading-edge technologies, theycan be assembled in an MCM according to the invention. In addition, thesubstrate described above can be used in repetition advantageously interms of cost reduction of bump forming as well as environmentally.

[0029] Conclusively, there are such advantages and effects according tothe present invention that because of the provision of the method ofmanufacturing the chip-like electronic components, comprising the stepsof: pasting on the substrate the adhesive material having the propertyto retain its adhesive strength prior to its processing and to lose itsadhesive strength after its processing; fixing on this substrate theplurality and/or the plurality of different types of semiconductor chipswith their electrode surfaces facing down; coating the whole area of thesemiconductor chips including the interspatial gaps therebetween withthe protective material; applying the predetermined processing to theadhesive material to lose its adhesive strength; peeling off the pseudowafer having the semiconductor chips which are bonded at their sidewalls and their bottom surfaces with the protective material; and dicingthe plurality of semiconductor chips from the pseudo wafer as requiredinto a discrete semiconductor chip or a chip-like electronic componentby cutting the protective material at the position between the pluralityof semiconductor chips, thereby the adverse effects such as strain,flash, crack damages or the like on the chip-like electronic componentsdue to dicing can be suppressed. Further, there is another merit that bydicing only the non-defective chip-like electronic components from thepseudo wafer and rearranging them on the package substrate, we canobtain the wafer as if having solely and only the non-defective chips,thereby enabling the wafer batch solder bump processing to be realized,allowing for the flip-chip solder bump chips to be formed at a low cost.Further, there is still another advantage that notwithstanding whetherthe bare chips are purchased from the other manufacturer or manufacturedin-house, easy and efficient solder bump processing becomes possible.Furthermore, because the side walls and bottom surfaces of respectivechips are covered with and protected by the protective material, Nielectroless plating processing becomes possible, and also an excellentpackaging reliability is ensured to be maintained in the subsequentpackage handling of the diced chips.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIGS. 1A-1K are cross-sectional views showing a flow of steps ofmanufacture of a semiconductor chip according to a first embodiment ofthe invention.

[0031]FIG. 2 is a cross-sectional view showing a pseudo wafer of theabove using a metal ball instead of a solder paste.

[0032]FIG. 3 is a perspective view of a quartz substrate having solelyand only non-defective (conforming) bare chips pasted thereon.

[0033]FIG. 4 is a perspective view of a large-sized glass substrate ofthe same on which only non-defective bare chips are pasted.

[0034] FIGS. 5A-5J are cross-sectional views showing a flow of steps ofmanufacture of a semiconductor chip for use in an MCM according to asecond embodiment of the invention.

[0035]FIG. 6 is a perspective view of a quartz substrate having solelyand only non-defective chips pasted thereon.

[0036]FIG. 7 is a perspective view of a large-scaled glass substratehaving solely non-defective chips pasted thereon.

[0037] FIGS. 8A-8G are cross-sectional views showing a flow of steps ofmanufacture of a wafer for use in the MCM according to a thirdembodiment of the invention.

[0038]FIG. 9 is a perspective view of an example of conventional Au studbumps.

[0039]FIG. 10 is a plan view in part of a semiconductor wafer subjectedto a batch solder bump treatment in a stage of its wafer level.

[0040] FIGS. 11A-11E are cross-sectional views showing a flow of stepsof manufacture of the semiconductor chip according to the above.

[0041]FIGS. 12A and 12B show a perspective view of an example of modulestructures packaged into an MCM (12A), and a side view of the same(12B).

[0042] FIGS. 13A-13C show a perspective view of another example ofmodule structures packaged into an MCM (13A), and side views of the same(13B and 13C).

[0043]FIG. 14 is a perspective view of a semiconductor wafercorresponding to the wafer batch processing.

PREFERRED EMBODIMENTS OF THE INVENTION

[0044] According to the present invention, the above-mentionedprotective material is an organic insulating resin or an inorganicinsulating material. The semiconductor chip of the invention which isdiced at the position of the protective material between respectivesemiconductor chips and mounted on a packaging substrate may be a singleor a plurality of chips, or a plurality of different types of chipswhich are integrated by means of the protective material, wherein theabove-mentioned electrodes are provided on the packaging surface thereofwhile the side wall and the bottom surface thereof are covered with theabove-mentioned protective material, and preferably solder bumps areformed on the above-mentioned electrodes.

[0045] Preferably, a single semiconductor chip or an integratedsemiconductor chip integrating a plurality of them or a plurality ofdifferent types of them to be mounted on a packaging substrate areobtained according to the invention by the method, comprising the stepsof: pasting an adhesive sheet on a flat surface of a transparentsubstrate or the like; fixing a plurality of non-defective (conforming)semiconductor chips or a plurality of different types of them on thisadhesive sheet, with the surfaces thereof having the electrodes facingdown; uniformly coating the semiconductor chips from their bottomsurfaces with the protective material which is the organic insulatingresin or inorganic insulating material and subsequently hardening thesame; then irradiating with ultraviolet rays from the bottom of thetransparent substrate opposite to its surface on which the semiconductorchips are fixed, or applying a chemical solution or heating so as toweaken the adhesive strength of the above-mentioned adhesive sheet;peeling off from the substrate a pseudo wafer having the plurality ofsemiconductor chips and/or the plurality of different types of thembonded thereon with the protective material; thereby obtaining thepseudo wafer which has a plurality of solely non-defective (conforming)semiconductor chips or a plurality of different types thereof arrayedthereon, and the surface thereof having the electrodes exposed; dicingthis pseudo wafer by cutting along the scribe line at the position ofthe protective material between the plurality of semiconductor chipsand/or the plurality of different types thereof; and acquiring discretesemiconductor chips and/or integrated semiconductor chips integrating aplurality of semiconductor chips or a plurality of different typesthereof ready to be mounted on the packaging substrate.

[0046] Further, the non-defective semiconductor chips or chip-likeelectronic components may be selected in such a manner that solely andonly the semiconductor chips which are judged to be non-defective bycharacteristics measurements are allowed to be bonded on theabove-mentioned substrate, or that they are subjected to thecharacteristics measurements in a state as bonded with theabove-mentioned protective material and then only the non-defectivesemiconductor chips or chip-like electronic components are selected.

[0047] Preferred embodiments of the invention will be described morespecifically in the following with reference to the accompanyingdrawings.

[0048] Embodiment 1

[0049]FIG. 3 shows an example of intermediate wafers having onlynon-defective semiconductor bare chips 3 (or LSI chips) that are dicedfrom the semiconductor wafer 53 indicated in FIG. 14, verified to beconforming to its specification in an open/shorted or DC voltagemeasurements, then arranged at an equidistance from each other andpasted on a circular quartz substrate 1 via an adhesive sheet 2 made ofacrylic or the like. Further, FIG. 4 shows another example thereofwherein a large-sized square glass substrate 19 is used instead of thecircular quartz substrate 1 in order to allow for a greater number ofnon-defective chips 3 to be pasted on a relatively limited area via theadhesive sheet 2, thereby ensuring an improved cost merit to be attainedin the subsequent processing.

[0050] A method of forming solder bumps in batch using the quartzsubstrate 1 of FIG. 3 on which only the non-defective chips are pastedwill be described in the following with reference to FIGS. 1A-1K.

[0051]FIG. 1A shows a quartz substrate 1 serving as a temporary supportsubstrate. However, because a heat process to be applied to thissubstrate is below 400° C., a less costly glass substrate may be used.Further, this quartz substrate 1 can be used in repetition.

[0052] In the next step of FIG. 1B, an adhesive sheet 2 made of such asacrylic which is used in a normal dicing and loses its adhesive strengthwhen irradiated with ultraviolet rays is pasted on the quartz substrate1.

[0053] In the next step as shown in FIG. 1C, a plurality ofnon-defective bare chips 3 verified to be conforming as described aboveare arrayed and pasted on the adhesive sheet 2 with their chip surfaces(device surfaces) 28 facing down. By way of example, these non-defectivebare chips 3 may be selected from a dicing sheet (not shown) which wassubjected to dicing in a wafer process and in an extended state, or maybe transferred from a chip tray. What is important and to be noted hereis that notwithstanding whether they are manufactured in-house or byother manufacturers, totally and only the non-defective bare chips 3 areallowed to be rearranged on the substrate 1.

[0054] Next, as shown in FIG. 1D, an organic insulating resin such as anacrylic resin 4 is coated uniformly on the chip 3 and a gaptherebetween. This coating can be attained easily by a spin coating orprinting methods.

[0055] In the next step as shown in FIG. 1E, ultraviolet rays areirradiated from a bottom side 31 of the quartz substrate 1 so as toweaken the adhesive strength of the adhesive sheet, then a pseudo wafer29 comprising a plurality of non-defective bare chips 3 which are bondedcontinuously on their side walls and bottom surfaces is peeled off fromthe quartz substrate 1 at an adhesive surface 30.

[0056] In the next step as shown in FIG. 1F, the pseudo wafer 29 isturned over so as to cause a non-defective bare chip's surface (devicesurface) 28 to face upward. The pseudo wafer 29 as partially enlarged inthis figure has an Al electrode pad 5 and a passivation film formed onthe silicon substrate via an SiO₂ film.

[0057] Then, as shown in FIGS. 1G-1I, the same steps of processing asalready described with reference to FIGS. 11C-11E are applied. FIG. 1Gshows an Ni electroless plating process to provide a UBM, FIG. 1H showsa print/transfer of a solder paste 9 using a print mask 8, and FIG. 1Ishows a state of a solder bump 12 formed by a wet back method.

[0058] Namely, in the step of FIG. 1G, only on a surface of the Alelectrode pad 5 which is opened, an Ni electroless plating layer (UBM)is formed selectively by the Ni electroless plating method. This Nielectroless plating layer (UBM) is easily formed by the steps of:pretreating the upper surface of the Al electrode pad 5 with aphosphoric acid etching solution; then precipitating Zn by a zincsubstitution process; and dipping in an Ni—P plating vessel. This Nielectroless plating layer functions as a UBM (under bump metal) whichfacilitates electric connection between the Al electrode pad 5 and thesolder bump.

[0059]FIG. 1H shows a state of a solder paste 9 which was transferredvia the print mask 8 onto the Ni electroless plated layer (UBM) by theprinting method. FIG. 1I shows a state in which the solder paste 9 isfused by the wet back method to form the solder bump 12. As describedabove, the solder bump 12 can be formed easily using the Ni electrolessplating method and the solder paste screen printing method or the like,without need of using a photo process.

[0060] According to the steps of fabrication described above, even ifthe chips to be fabricated are leading-edge LSIs which normally have alow yield, or purchased from the other manufacturers, if totally andonly non-defective chips 3 selected from among them are rearranged andpasted on the quartz substrate 1 to provide for a pseudo wafer 29 whichis thus comprised, as if, totally of non-defective bare chips 3, a waferbatch bump forming becomes possible, thereby decreasing the fabricationcost substantially.

[0061] Further, in the step of FIG. 1I, by carrying out measurements ofelectrical characteristics of the non-defective chips by a probeinspection and/or a burn-in processing, a more precise selection only ofthe non-defective bare chips 3 which passed prior selection before thestep of FIG. 1C will be ensured.

[0062]FIG. 1J shows a step of dicing the pseudo wafer 29 along a scribeline 33 with a blade 32 (or a laser beam) into discrete pieces of anon-defective chip component 26 which is comprised of the chip 3 whichis protected and enforced by the resin 4.

[0063] Then, as shown in FIG. 1K, the non-defective chip component 26diced into a discrete piece is mounted on a package substrate 27 whichis provided with an electrode 14 which is surrounded by a solder resist15 on a wiring substrate 16, and covered with a solder paste 13.

[0064] In this instance, because the side wall and the bottom surface ofthe non-defective chip component 26 are covered with the resin 4, nodamage direct to the non-defective chip component 26 occurs during anadsorption handling or the like when mounting the same on the packagingsubstrate 27. Therefore, a high reliability flip chip packaging isexpected to be done.

[0065] The above description has been made by way of example of the flipchip packaging technique for packaging semiconductor chips, however, itis not limited thereto, and may be applied to an interconnection solderbump forming technique in a high density flip chip packaging and amethod of fabrication thereof, wherein the non-defective bare chips 3are arrayed at an equidistance and pasted on the quartz substrate 1 withtheir surfaces (device surface) 28 facing downward, then the resin 4 iscoated uniformly on their bottom surfaces and therebetween therebysecuring the non-defective chips 3 to be held firmly to each other.

[0066] By peeling off from the adhesive sheet 2, the pseudo wafer 29 onwhich only non-defective chips 3 are arrayed is provided, then a batchbump forming on this pseudo wafer 29 is carried out thereby allowing alow cost bump chip to be fabricated. This bump chip of the invention canbe used not only in compact, lightweight and portable electronicdevices, but also in any other types of electronic devices.

[0067]FIG. 2 shows a modified type of the bump forming method in which ametal ball (solder ball) 17 is used in place of the above-mentionedsolder paste 9.

[0068] Namely, a passivation film which covers the Al electrode pad 5formed on the pseudo wafer is perforated at a position where a bumpelectrode is to be formed, and a Ni electroless plating layer (UBM) isformed therein.

[0069] Then, a flux 18 is coated on this Ni electroless plated layer(UBM) by a printing method or the like. A material suitable for thisflux 18 preferably has a high adhesive strength so as to facilitate atransfer of a metal ball 17, and a quantity of this coating issufficient if the metal ball 17 is retained. By way of example, althoughthe method for coating the flux 18 is not limited to the printingmethod, however, in practice, the printing method is preferable. It isbecause that in comparison with the other methods, this method isadvantageous in that it can coat the flux 18 in a preferred pattern in asimple and efficient operation.

[0070] Further, the metal ball 17 which is mounted on the flux 18 issubjected to a reflow (fusing) process, and then the flux 18 is cleaned.Thereby, the metal ball 17 is ensured to attach to the Ni electrolessplating layer (UBM) very strongly, thereby completing the process offorming bump electrodes.

[0071] As described hereinabove, according to the first embodiment ofthe present invention, because that the non-defective semiconductorchips diced from the wafer are rearranged and pasted on the substrate atthe equidistance, then after coating with the resin, the pseudo wafer asif having totally and only the non-defective semiconductor chips isobtained. Therefore, the wafer batch processing for forming solder bumpson the plurality of the non-defective chips becomes possible, therebyenabling a chip having flip chip solder bumps to be formed at a lowcost. Further, not only the wafers of the in-house product but also barechips purchased from the other manufacturers can be processed alike toform solder bumps thereon easily according to the invention.

[0072] Still further, because that the side walls and the bottomsurfaces of respective chips are covered with the resin and protectedthereby, even the Ni electroless plating process becomes possible, andthus an excellent package reliability is ensured even in a packagehandling of respective chips after diced into discrete chips. Becausethe substrate used for pasting non-defective chips can be usedrepeatedly after peeling the pseudo wafer, it is advantageous for costreduction of the bump forming and environmental protection.

[0073] Furthermore, the merit and the advantage of the low cost bumpprocessing based on the wafer batch processing method of the inventioncan be utilized in processing of the leading-edge LSIs or bare chipspurchased from the other manufacturer, thereby providing a novel bumpforming method widely applicable. In addition, when dicing respectivesemiconductor chips from the pseudo wafer after treatment, because theyare cut along the scribe line at the position of the resin betweenrespective chips, the dicing is carried out easily without damaging thecutter blade and minimizing adverse effects (strain, flash, crack andthe like damages) on the body of the semiconductor chips.

[0074] Embodiment 2

[0075] FIGS. 5-7 show a second embodiment of the present invention forobtaining chip-like electronic components each packaged in an MCM (multichip module) comprising a plurality of different types of non-defectivechips.

[0076] Namely, FIGS. 5A-5J correspond respectively to FIGS. 1A-1J of thefirst embodiment described hereinabove, wherein the same components withthe same reference numerals are omitted of their explanations, and theprocess of FIG. 1K is executed in the same manner also in this secondembodiment.

[0077] According to the second embodiment, in the step of FIG. 5C, asthe semiconductor chips 3, a plurality of different types ofsemiconductor chips 3 a and 3 b are pasted on the quartz substrate 1,then they are treated in the same manner as described in the firstembodiment. However, as shown in FIG. 5J, the plurality of differenttypes of semiconductor chips 3 a and 3 b are scribed into variouspatterns of combinations thereof, and diced into non-defective chip-likecomponents 26 for providing MCMs.

[0078]FIG. 6 shows an example of equidistantly re-arranged plurality ofdifferent types of semiconductor chips 3 a and 3 b (or LSI chips) whichare diced from the semiconductor wafer, verified to be conforming(non-defective) in an open/short-circuited or DC voltage measurements,and pasted on a circular quartz substrate 1 via the adhesive sheet 2made of acrylic or the like. FIG. 7 shows another example of the abovein which a greater number of non-defective chips 3 are pasted via theadhesive sheet 2 on a larger-sized square glass substrate 19 which isused in place of the circular quartz substrate 1 so as to allow for thegreater number of non-defective chips to be pasted on a limited area,thereby allowing for an increased cost merit to be attained in thesubsequent processing.

[0079] The same advantages and effects as in the first embodiment areobtained according to the second embodiment as well, and this embodimentis confirmed suitable for provision of the MCMs.

[0080] Embodiment 3

[0081] With reference to FIGS. 8A-8G, a third embodiment of the presentinvention is described, in which a SOG (spin on glass) film 4′ whichconsists of an inorganic insulating material such as SiO_(x) is usedinstead of the resin 4 used in the first embodiment for embedding thenon-defective chips 3, then after heating or the like, a pseudo wafer 29for use in fabrication of MCMs is peeled off.

[0082] Namely, FIG. 8A depicts a substrate 1′ which serves as atemporary support substrate. However, the substrate 1′ used here is notlimited to the above-mentioned quartz substrate or the glass substrate,but other non-transparent substrates such as Si or a metal plate may beused alike.

[0083] Then, as shown in FIG. 8B, an adhesive sheet 2′ made of, forexample, acrylic, which is used in normal dicing and has a property tolose its adhesive strength when subjected to a chemical solution orheating is pasted on the substrate 1′.

[0084] Further, as shown in FIG. 8C, a plurality of semiconductor barechips 3 which are confirmed to be non-defective and conforming asdescribed hereinabove are arrayed and pasted on the adhesive sheet 2′with their chip surfaces (device surfaces) 28 facing downward. By way ofexample, the plurality of non-defective bare chips 3 used here may beselected directly from an extended dicing sheet (not shown) used indicing in the normal wafer process as shown in FIG. 14, or may betransferred from a chip tray. What is important and should be note hereis that notwithstanding whether they are in-house products or thosepurchased from outside, totally and only the non-defective or conformingbare chips 3 are allowed to be rearranged on the substrate 1.

[0085] Preferably, this non-defective chip 3 is specially designedsuitable for a multi chip module packaging. Further, preferably, thesame has a small pad (approximately ≦20 nm□) for inter-chip wiring, anda test pad for testing each chip.

[0086] In the next step of FIG. 8D, the insulating material 4′ such asSOG or the like is coated from above the chips 3 thereby embedding thechips 3.

[0087] Then, in the step of FIG. 8E, after bonding a Si wafer 70 on theinsulating material 4′, the adhesive strength of the adhesive sheet 2′is weakened by applying a chemical solution or heating so as to allowfor both of the Si wafer 70 and the embedded chips 3 firmly retained bythe adhesive strength of the insulating material 4′ to be removed fromthe substrate 1′ as depicted in FIG. 8F.

[0088] Through these steps of processing described hereinabove, aplurality of module chips 3 having a uniform level of surface height areensured to be bonded on the Si wafer 70. Subsequently, re-wiring betweenthe chips 3 is carried out in the normal wafer process as indicated inFIG. 8G.

[0089] Thereby, a problem associated with the conventional technique ofrewiring between respective module chips resulting from a difference inheights of chips is solved by provision of the flattened wiring surfacesof the chips according to the invention, thereby allowing the rewiringtherebetween to be accomplished for sure. Namely, in the conventionalMCM packaging technique in which the semiconductor or LSI chips aremounted on the Si wafer and rewired therebetween, there was a problemdue to variations in film thickness between respective module chips, andactually it has been difficult to adopt a method of rewiring whichutilizes any of the preceding steps of handling. However, according tothe embodiments of the invention, it is enabled to paste the pluralityof chips 3 on the Si wafer with their surface heights leveled uniformlyin a horizontal direction without need of consideration of thevariations in the film thickness of respective module chips, therebysubstantially simplifying and facilitating the rewiring process of theMCMs.

[0090] Further, after the step of FIG. 8G, the packaging process mayproceed in the same flow of steps as indicated in FIGS. 1I-1K.

[0091] The present invention is not limited to the preferred embodimentsdescribed above, and many other modification can be contemplated withinthe scope of the invention.

[0092] For example, the substrate on which the non-defective bare chipsare to be pasted may be comprised of any other materials instead of thequartz or glass if it has the same function and strength. Further, theshape and thickness of its substrate can be modified at discretion.Also, various types of acrylic or other materials may be used as theadhesive sheets 2 and 2′ if it has the same function. Materials for theresin 4 and insulating material 4′ may be selected from the groupconsisting of the similar materials. In addition, the distance betweenthe plurality of non-defective bare chips 3 at which they are arrayedmay be selected at discrete if it is equidistant.

[0093] Further, the substrate such as the quartz substrate 1 describedheretofore can be used repeatedly thereby providing substantialadvantages in cost merits and environmental protection. Still further,the object of application of the invention is not limited to thesemiconductor chips described hereinabove, but is also applicable to anyother chip-like electronic components which involve the process ofdicing into discrete chips during its fabrication.

What is claimed is:
 1. A chip-like electronic component having at leastits electrodes formed exclusively on one surface thereof, and surfacesother than said one surface are continuously covered with a protectivematerial.
 2. The chip-like electronic component according to claim 1wherein said protective material comprises an organic insulating resinor an inorganic insulating material.
 3. The chip-like electroniccomponent according to claim 1, comprising a semiconductor chip dicedfrom a wafer at a position of said protective material for mounting on apackage substrate, wherein said electrode is formed on said one surface,which is a device surface, of said semiconductor chip, and both a sidewall and a bottom surface of said semiconductor chip are covered withsaid protective material.
 4. The chip-like electronic componentaccording to claim 3 wherein a solder bump is formed on said electrode.5. The chip-like electronic component according to claim 1 wherein aplurality and/or a plurality of different types of semiconductor chipsare integrated as bonded by said protective material.
 6. A pseudo wafercomprising a plurality and/or a plurality of different types ofchip-like electronic components having at least their electrodes formedsolely on one surface thereof, wherein interspaces between saidplurality and/or said plurality of different types of chip-likeelectronic components and bottom surfaces thereof are continuouslycovered with said protective material, and bonded with each other. 7.The pseudo wafer according to claim 6 wherein said protective materialcomprises either one of an organic insulating resin and an inorganicinsulating material.
 8. The pseudo wafer according to claim 6 whereinsaid plurality and/or said plurality of different types of semiconductorchips arrayed thereon are diced at a position of said protectivematerial between said plurality of semiconductor chips and fabricatedinto a discrete chip or an integrated semiconductor chip integrating aplurality and/or a plurality of different types of semiconductor chipsto be mounted on a packaging substrate.
 9. The pseudo wafer according toclaim 8 wherein a solder bump is formed on said electrode.
 10. A methodof manufacturing a chip-like electronic component, comprising the stepsof: pasting an adhesive material on a substrate, said adhesive materialhaving a property to retain an adhesive strength prior to a processingand to lose said adhesive strength after said processing; fixing aplurality and/or a plurality of different types of semiconductor chipson said adhesive material with an electrode surface thereof facing down;coating a whole area including said plurality and/or said plurality ofdifferent types of semiconductor chips and interspaces therebetween witha protective material; applying a predetermined process to said adhesivematerial to weaken said adhesive strength of said adhesive material soas to peel off a pseudo wafer which bonds said plurality and/or saidplurality of different types of semiconductor chips as covered with saidprotective material; and dicing said plurality and/or said plurality ofdifferent types of semiconductor chips by cutting said protectivematerial in said interspaces therebetween thereby obtaining a discretesemiconductor chip or a chip-like electronic component.
 11. The methodof manufacturing chip-like electronic components according to claim 10,wherein: said substrate has a flat surface; said adhesive material is anadhesive sheet; said plurality and/or said plurality of different typesof semiconductor chips are non-defective; said protective material iseither one of an organic insulating resin and an inorganic insulatingmaterial and is uniformly coated on said plurality of semiconductorchips from a bottom surface thereof to be hardened; said predeterminedprocess includes irradiating ultraviolet rays on said adhesive sheetthrough said flat substrate from a bottom surface thereof opposite tothe surface bonding said plurality of semiconductor chips, or applying achemical solution or heating the same to weaken said adhesive strengthof said adhesive sheet so as to peel off a pseudo wafer having saidplurality and/or said plurality of different types of semiconductorchips bonded thereon as covered with said protective material, from saidflat substrate, thereby obtaining said pseudo wafer, wherein saidplurality and/or said plurality of different types of semiconductorchips which are totally non-defective (conforming) are arrayed thereonwith their electrode surfaces exposed; and dicing said pseudo waferbetween said plurality and/or said plurality of different types ofsemiconductor chips.
 12. The method of manufacturing the chip-likeelectronic components according to claim 10, wherein: said pseudo waferis diced at a position of said protective material between saidplurality and/or said plurality of different types of semiconductorchips; and a discrete semiconductor chip or an integrated chipintegrating a plural number and/or a plural different types ofsemiconductor chips to be mounted on a package substrate are obtained.13. The method of manufacturing the chip-like electronic componentsaccording to claim 12, wherein a solder bump is on said electrodes. 14.The method of manufacturing the chip-like electronic componentsaccording to claim 10, wherein said plurality of semiconductor chipswhich are determined to be non-defective in a characteristic measurementthereof are fixed firmly on said substrate.
 15. The method ofmanufacturing the chip-like electronic components according to claim 10,further comprising the steps of: carrying out a characteristicmeasurement of said plurality of semiconductor chips in a state firmlyfixed thereon and bonded with said protective material; and selectingnon-defective semiconductor chips or non-defective chip-like electroniccomponents.
 16. A method of manufacturing a pseudo wafer comprising thesteps of: pasting an adhesive material on a substrate, said materialhaving a property to retain an adhesive strength prior to a processingand lose said adhesive strength after said processing; fixing on saidadhesive material a plurality and/or a plurality of different types ofsemiconductor chips with their electrode surfaces facing down; coatingwith a protective material a whole area of said plurality and/or saidplurality of different types of semiconductor chips includinginterspaces therebetween; applying a predetermined process to saidadhesive material so as to lose its adhesive strength; and peeling off apseudo wafer having said plurality and/or said plurality of differenttypes of semiconductor chips fixed thereon.
 17. The method ofmanufacturing said pseudo wafer according to claim 16, wherein: saidsubstrate has a flat surface; said adhesive material is an adhesive;said plurality and/or said plurality of different types of semiconductorchips are non-defective; said protective material is either one of anorganic insulating resin and an inorganic insulating material and inuniformly coated on said semiconductor chips from their bottom surfacesto be hardened; said predetermined process includes irradiatingultraviolet rays, through said substrate, on said adhesive sheet from abottom surface thereof opposite to the surface thereof fixing saidplurality and/or said plurality of different types of semiconductorchips thereon, or applying a chemical solution thereto or heating saidadhesive sheet to weaken the adhesive strength of said adhesive sheet soas to peel off a pseudo wafer having said plurality and/or saidplurality of different types of semiconductor chips bonded with saidprotective material from said substrate; and thereby said pseudo waferhaving said plurality and/or said plurality of different types ofsemiconductor chips which are non-defective, and arrayed thereon, withtheir electrode surfaces exposed is obtained.
 18. The method ofmanufacturing the pseudo wafer according to claim 16, wherein a solderbump is formed on said electrode.
 19. The method of manufacturing thepseudo wafer according to claim 16, wherein said semiconductor chipswhich are determined to be non-defective in characteristic measurementsthereof is fixed on said substrate.
 20. The method of manufacturing thepseudo wafer according to claim 16, further comprising the steps of:carrying out characteristic measurements of said semiconductor chips ina state as bonded with said protective material; and selectingnon-defective semiconductor chips or non-defective chip-like electroniccomponents.